CPU Accounting in CMP Processors

CPU power management for SMT and CMP processors

Cache optimization for CPU - GPU heterogeneous processors ∗

Microprocessors combining CPU and GPU cores using a common last-level cache pose new challenges to cache management algorithms. Since GPU cores feature much higher data access rates than CPU cores, the majority of the available cache space will be used by GPU applications, leaving only very limited cache capacity for CPU applications, which may be disadvantageous for overall system performance....

An Efficient CPU Architecture for DSP Processors

Design narrative of an efficient CPU architecture dedicated to UTS-DSP (University of Tehran and Iran Communication Industries(SAMA) DSP) [1]-[10] is reported. Time and area consuming, the CPU architecture is a critical component of the overall architecture, which is responsible for execution of arithmetic and logical operations. The goal is composing an optimized hardware appropriate for execu...

Thread allocation in CMP-based multithreaded network processors

Article history: Received 28 July 2008 Received in revised form 3 August 2009 Accepted 11 January 2010 Available online 20 January 2010

Integrated CPU Cache Power Management in Multiple Clock Domain Processors

Multiple clock domain (MCD) chip design addresses the problem of increasing clock skew in different chip units. Importantly, MCD design offers an opportunity for fine grain power/energy management of the components in each clock domain with dynamic voltage scaling (DVS). In this paper, we propose and evaluate a novel integrated DVS approach to synergistically manage the energy of chip component...